1. Field of the Invention
The present invention relates to a semiconductor memory device and a data write method, and more specifically to a semiconductor memory device including a plurality of memory cells and a method for writing data to such a semiconductor memory device.
2. Description of the Related Art
Recently, semiconductor memory devices such as, for example, non-volatile memories have significantly improved in performance in terms of the degree of integration, data processing rate and the like. Especially, a flash memory which is a non-volatile memory is widely used in compact information devices for personal terminals, for example, cellular phones. Flash memory is one type of EEPROM (Electrically Erasable Programmable Read Only Memory). A flash memory includes a plurality of memory cells. Each memory cell includes a MOS transistor having a floating gate which is electrically separated from the other elements in the memory cell.
FIG. 8 is a schematic cross-sectional view of a memory cell 100 included in a flash memory.
As shown in FIG. 8, the memory cell 100 includes a semiconductor substrate 101, a drain region 102 and a source region 103. The drain region 102 and the source region 103 are provided on the semiconductor substrate 101. The drain region 102 and the source region 103 have a prescribed distance therebetween. The source region 103 and the drain region 102 are doped with dopants (impurity elements) which generate different conductivities. Surfaces of the drain region 102, the source region 103, and a portion of the semiconductor substrate 101 between the drain region 102 and the source region 103 are covered with a first insulating layer 104 which is a gate insulating layer. Above the portion of the semiconductor substrate 101 between the drain region 102 and the source region 103, a floating gate 105 formed of polysilicon, a second insulating layer 106 formed of SiO2, and a control gate 107 formed of polysilicon are sequentially provided. The first insulating layer 104 is interposed between the semiconductor substrate 101 and the floating gate 105. In a final state of the memory cell 100, both of two side surfaces of the floating gate 105 are covered with an insulating layer (not shown), and thus the floating gate 105 is in an electrically floating state. The second insulating layer 106 electrically separates the floating gate 105 and the control gate 107.
Generally in the field of flash memory, injection of hot electrons, generated in a channel region between the drain region 102 and the source region 103 in the memory cell 100, into the floating gate 105 is associated with writing of data to the memory cell 100 (programming).
More specifically, when a high electric field is applied to between the drain region 102 and the source region 103, a large magnitude of current flows in the channel region. As a result, hot electrons are generated in a portion in the channel region which is close to the drain region 102 and has a high electric field. The hot electrons are injected into the floating gate 105, and charges are accumulated in the floating gate 105. This changes the threshold voltage (Vth) as a transistor characteristic of the MOS transistor included in the memory cell 100 and data is written to the memory cell 100. The threshold voltage (Vth) is defined as a minimum voltage, applied to the control gate 107, which is required to put the channel region between the source region 103 and the drain region 102 into a conductive state. The threshold voltage (Vth) is controlled by the amount of charge accumulated in the floating gate 105.
FIG. 9 schematically shows voltage conditions for writing data to the memory cell 100 shown in FIG. 8.
For writing data to the memory cell 100, a program voltage of about 12 V is applied to the control gate 107, a drain voltage of about 6 V is applied to the drain region 102, and a reference voltage of 0 V is applied to the source region 103 and the channel region in the semiconductor substrate 101 (as shown in FIG. 8).
Under such voltage conditions, the hot electrons generated as described above, in the portion having the high electric field, are injected into the floating gate 105 through the first insulating layer 104 by the program voltage of about 12 V applied to the control gate 107. The floating gate 105 is charged negative. As a result, the memory cell 100 is put into a data write (program) state.
In the data write (program) state, the hot electrons are collected in to the floating gate 105 and the threshold voltage (Vth) of the memory cell 100 is increased. Thus, the threshold voltage (Vth) of the memory cell 100 becomes a threshold voltage in the data write (program) state. When the above-mentioned voltage conditions are changed to remove the electrons (negative charges) from the floating gate 105 and thus lower the threshold voltage (Vth) of the memory cell 100, the memory cell 100 is put into a data erase state.
FIG. 10 is a graph illustrating a threshold voltage distribution of memory cells included in a general 2-value flash memory.
The horizontal axis represents the threshold voltage (Vth) of the memory cells, and the vertical axis represents the number of the memory cells. In FIG. 10, the reference threshold voltage at the center of the horizontal axis represents the read voltage which is applied to a control gate of each memory cell for reading data from the memory cell.
Generally in a 2-value flash memory, the state in which the electrons (negative charges) are removed from the floating gate of the memory cell is the data erase state, and such a state is associated with data “1”. The state in which the electrons are injected to the memory cell is the data write state, and such a state is associated with data “0”.
In FIG. 10, the portion of the graph with the threshold voltage lower than (to the left of) the reference threshold voltage shows a distribution of the data erase threshold voltage representing the threshold voltage of memory cells in the data erase state, and the portion of the graph with the threshold voltage higher than (to the right of) the reference threshold voltage shows a distribution of the data write threshold voltage representing the threshold voltage of memory cells in the data write state.
As shown in FIG. 10, the memory cells in the data erase state have a low threshold voltage and the memory cells in the data write state have a high threshold voltage. Accordingly, where an equal voltage is applied to the control gate of each memory cell, the memory cells in the data erase state have a larger magnitude of current flowing therethrough than the memory cells in the data write state. Thus, utilizing the fact that the current value of the memory cells in the data erase state is different form the current value of the memory cells in the data write state, it can be checked whether data is present in a memory cell or not (state of data). Such a checking operation is referred to as a data read operation or a data verifying operation.
In the data read operation or the data verifying operation, a reference cell in which the prescribed reference voltage is set is compared with a memory cell to be checked.
Specifically, the value of current flowing in the reference cell is compared with the value of current flowing in the memory cell to be checked. By comparing the values of the currents, data can be read.
More specifically, the value of current flowing in the bit line connected to the memory cell and the value of current flowing in the bit line connected to the reference cell are detected by a sense amplifier, and the values of these currents are compared. Thus, it is determined whether data is present in the memory cell or not.
In a flash memory, the data write threshold voltage can be changed to a prescribed value by controlling the amount of charge accumulated in the floating gate 105 in the memory cell 100 shown in FIG. 8. Thus, data of multi-value information which is different from the previously processed information can be written.
FIG. 11 is a graph illustrating an exemplary threshold voltage distribution of memory cells included in a multi-value flash memory which is capable of writing multi-value data. For the sake of simplicity, FIG. 11 shows the distribution in the case of a 4-value flash memory in which one memory cell can store 2-bit data.
In FIG. 11, the horizontal axis represents the threshold voltage of memory cells and the vertical axis represents the number of the memory cells. Reference threshold voltages A, B and C each represent a data read voltage applied to the control gates of the memory cells for reading data.
Each memory cell in the 4-value flash memory can be selectively in one of four states, i.e., one data erase state and three data write states. The four states correspond to the four threshold voltage distributions of the memory cells. The lowest threshold voltage corresponds to the data erase state, and the other three threshold voltages correspond to the data write states. When a memory cell can be selectively in one of these four states, the three reference voltages A, B and C are set as shown in FIG. 11 for the data read operation of confirming the presence of data in the memory cells.
In the memory cells shown in FIG. 11, each memory cell can store 2-bit data. The data corresponding to the lowest threshold voltage distribution is defined as “11”. The data corresponding to the second lowest threshold voltage distribution is defined as “10”. The data corresponding to the third lowest threshold voltage distribution is defined as “01”. The data corresponding to the highest threshold voltage distribution is defined as “00”. Data “11” represents the data erase state. In the data write states in which data is defined as “10”, “01” and “00”, the range of the threshold voltage distribution corresponding to each level of data is narrower than that in the case of a 2-value flash memory shown in FIG. 10. Therefore, the amount of charge in the floating gate is accurately controlled such that the variance in each threshold voltage distribution is sufficiently small.
As shown in FIG. 11, a multi-value flash memory capable of storing multi-value information can increase the memory capacity without increasing the number of memory cells. Therefore, the use of such a multi-value flash memory is effective for increasing memory capacity or for reducing the size of the circuit for an equal memory capacity.
FIG. 12 is a flowchart of a data write operation (programming) performed to a flash memory as shown in FIG. 10 or 11 (see, for example, U.S. Pat. No. 5,440,505). Although not shown, each memory cell is connected as follows. The control gate is connected to a prescribed word line WL, and the drain region is connected to a prescribed bit line BL. The memory cells are arranged in a matrix.
The data write operation is performed as follows.
First, a memory cell in the data erase state is selected, and a data write operation to the selected data is started (step S501).
Next, first data write (program) voltages are set as follows (step S502).                (1) Vwl=V01 (voltage to be applied to the word line WL)        (2) Vbl=V02 (voltage to be applied to the bit line BL)        (3) t=t01 (voltage pulse width of Vwl and Vbl)        
For example, in a 4-value flash memory, the voltages are applied as follows: Vwl=8.0 V and Vbl=5.0 V. In a 2-value flash memory, Vwl=12.0 V is applied. In the 4-value flash memory, the voltage Vwl can be reduced to 8.0 V since the fluctuation of the threshold voltage (Vth) of each memory cell corresponding to each level of data in the 4-value flash memory is smaller than in the 2-value flash memory. Since the voltage Vwl can be lower, the load on the charge pump circuit for generating a high voltage can be alleviated.
Next, the first data write voltages of Vwl and Vbl are applied to the selected memory cell, and the voltages are held for voltage pulse width t01 (step S503).
Then, a verifying operation is performed on the threshold voltage of the memory cell to which data has been written (step S504). As described above, the verifying operation is an operation for checking the threshold voltage of a memory cell to confirm whether or not data (information) has been written to the memory cell as expected.
When the threshold voltage of the memory cell to which data has been written is in a prescribed range (YES in step S505), the data write operation is completed (step S506). When the threshold voltage of the memory cell to which data has been written has exceeded the prescribed range (YES in step S507), the data write operation to the memory cell results in a failure (step S508). When the threshold voltage of the memory cell to which data has been written has not yet reached the prescribed range (NO in step S507), the data write voltages are applied again to the memory cell and the verifying operation is performed again.
When the threshold voltage of the memory cell has not yet reached the prescribed range, the first data write voltage Vwl is increased by a prescribed voltage value (ΔV), for example, 0.5 V, to Vwl=8.5 V (step S509).
Next, second data write (program) voltages are set as follows (step S510).                (1) Vwl=V03 (=V01+ΔV) (in step S509)        (2) Vbl=V02        (3) t=t02 (t02<t01)        
Voltage width t02 of the second data write voltages is set to be shorter than the voltage pulse width of the first data write voltages, and the time period in which the second data write voltages are applied is shorter than the time period in which the first data write voltages are applied.
Next, until the second data write voltage Vwl, and the number of times that the data write operation to the memory cell (programming) has been performed, both reach the maximum values (steps S511 and S512), steps S503 through S512 are repeated such that the threshold voltage in the memory cell reaches the prescribed range.
When the second data write voltage Vwl, and the number of times that the data write operation to the memory cell (programming) has been performed, both reach the maximum values (YES in steps S511 and S512), the data write operation to the memory cell results in a failure (step S508). As shown in steps S507 and S508, when the threshold voltage of the memory cell to which data has been written has exceeded the prescribed range (YES in step 507), 1-bit data cannot be erased because of the flash memory cell array structure. Therefore, the data write operation to this memory cell results in a failure.
There is a tendency that memory capacity of flash memories is desired to be increased. For example, as the level of multi-value information increases from 4 (4-value information) to 16 (16-value information), the range of the threshold voltage distribution of the memory cells corresponding to each level of data is further narrowed. Therefore, even when a data write operation to memory cells is performed with an extreme care in accordance with the flowchart shown in FIG. 12, it is possible that the threshold voltage of a memory cell has exceeded the prescribed range of the threshold voltage threshold distribution due to, for example, the variance in the transistor characteristics of the MOS transistor included in the memory cell, and as a result, incorrect data is written to the memory cell.
In this case, it is necessary to erase the data (information) in the memory cell and perform the data write operation again. In a flash memory, due to its cell array structure, data erase is performed block by block, each block including a plurality of memory cells. Therefore, when incorrect data is written to one memory cell in a certain block, it is necessary to (i) first write the data, which has been written to the other memory cells in the same block, to the memory cells in another block, (ii) erase the data in the certain block, and then (iii) write back the data, which has been written to the another block, to the memory cells in the certain block.
Generally in a flash memory, data can be erased from a memory cell in a time period in the order of milliseconds, whereas data can be written into a memory cell in a time period in the order of microseconds. Data erase is significantly more time-consuming than data write. Accordingly, use of the above-described method to write data to each memory cell in the flash memory significantly extends the time necessary to complete the data write operation (programming).